MENTOR_BENCH · AMAZON · NXP · MARVELL · MATHWORKS · QUALCOMM · NVIDIA

Meet the industry mentors

Working engineers from semiconductor product and EDA companies who review your work, run your mocks and open their networks to you. Every mentor is verified by the Silicawafer team.

Arjun Verma — Founder & Lead Mentor — ASIC Design Verified mentorEx-Marvell Technology

Arjun Verma

Founder & Lead Mentor — ASIC Design

RTL Design & Verification5+ yrs

Designed and verified SOC IP blocks that shipped in enterprise storage silicon. Arjun personally maps every mentee's week-by-week plan and joins the final mock interview.

Srinivas Rao — Senior Staff Engineer — Physical Design Verified mentorNXP Semiconductors

Srinivas Rao

Senior Staff Engineer — Physical Design

Physical Design12+ yrs

Closed timing on automotive SoC blocks at 16nm and 7nm. Srinivas teaches the PD flow the way teams actually run it — constraints first, tools second.

Rahul Menon — Senior Engineer — RTL Verification Verified mentorAmazon Annapurna Labs

Rahul Menon

Senior Engineer — RTL Verification

RTL Design & Verification7+ yrs

Builds UVM environments for custom silicon that powers AWS infrastructure. Famous among mentees for making assertions finally make sense.

Kavya Iyer — Lead Engineer — Design for Test Verified mentorMarvell Technology

Kavya Iyer

Lead Engineer — Design for Test

Design for Test (DFT)9+ yrs

Owns DFT architecture for networking SoCs. Kavya reviews mentee ATPG projects line by line until coverage closure becomes muscle memory.

Nikhil Reddy — Senior Application Engineer — Model-Based Design Verified mentorMathWorks

Nikhil Reddy

Senior Application Engineer — Model-Based Design

Embedded & FPGA6+ yrs

Helps chip teams simulate and generate hardware from MATLAB/Simulink models. Nikhil covers the embedded lane and the math behind it.

Sneha Kulkarni — Staff Engineer — Analog & Mixed-Signal Layout Verified mentorMarvell Technology

Sneha Kulkarni

Staff Engineer — Analog & Mixed-Signal Layout

Analog & Mixed-Signal Layout10+ yrs

Laid out high-speed SerDes and PLL blocks across five process nodes. Sneha teaches matching, parasitics and the quiet art of clean analog floors.

Vikram Shetty — Senior Engineer — Design Verification Verified mentorQualcomm

Vikram Shetty

Senior Engineer — Design Verification

RTL Design & Verification8+ yrs

Verifies camera & compute IPs that ship in billions of phones. Vikram runs our regression-themed mock interviews and referral drives.

Divya Nair — Principal Engineer — STA & Signoff Verified mentorCadence Design Systems

Divya Nair

Principal Engineer — STA & Signoff

Physical Design11+ yrs

Signs off timing methodology used by dozens of tape-outs. Divya demystifies multi-mode multi-corner STA until it feels like arithmetic.

HOW_A_1:1_WORKS

01

Pick your mentor & slot

Choose the engineer whose domain matches your goal, and a slot that fits your college timetable.

02

Share your profile & goals

Send your semester, subjects you enjoyed, current skills and target companies — your mentor comes prepared.

03

Get your week-by-week plan

Leave the call with a personalized roadmap, the projects to build first and honest feedback on your gaps.